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VS-702
Voltage Controlled SAW Oscillator Previous Vectron Model VS-720
VS-702
Description
The VS-702 is a SAW Based Voltage Controlled Oscillator that achieves low phase noise and very low jitter performance. The VS702 is housed in an industry standard hermetically sealed LCC package and available in tape and reel.
Features
* * Industry Standard Package, 5.0 x 7.5 x 2.0 mm ASIC Technology for Ultra Low Jitter 0.100 ps-rms typical across 12 kHz to 20 MHz BW 0.120 ps-rms typical across 50 kHz to 80 MHz BW * * * * * * * Output Frequencies from 150 MHz to 1 GHz 3.3 V Operation LV-PECL or LVDS Configuration with Fast Transition Times Improved Temperature Stability over Standard VCSO (20 ppm) Output Disable Feature 0/70C or -40/85C operating temperature Product is free of lead and compliant to EC RoHS Directive * * * * *
Applications
Ideal for PLL circuits for clock smoothing and frequency translation
SONET, SDH Synchronous Ethernet Fiber Channel LAN / WAN Test and Measurement
Block Diagram
Complementary Output Output VDD
BAW
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SAW
VC
E/D
Gnd
Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
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Performance Specifications
Table 1. Electrical Performance Parameter
Voltage1 Current (No Load) Nominal Frequency Linearity3 Gain Transfer Positive (See pg 5) Temperature Stability3 Mid Level
3 3 2
Symbol
VDD IDD
Min
Supply 2.97 Frequency
Typical
3.3 55
Maximum
3.63 70 1000
Units
V mA MHz ppm % ppm/V ppm
fN APR Lin KV fSTAB
150 50 5 +100 20 Outputs VDD-1.5 VDD-1.3 750 1.5
Absolute Pull Range 3,6
10
VDD-1.2
V mV-pp V-pp
Single Ended Swing3 Double Ended Swing3 Current Rise Time4 Fall Time4 Symmetry3 Jitter (12 kHz - 20 MHz BW)622.08MHz Period Jitter, RMS (622.08MHz)7 Period Jitter, Peak - Peak (622.08MHz) Spurious Suppression2 Control Voltage Control Voltage Range for APR Control Voltage Input Impedance Control Voltage Modulation BW Output Enabled, Option A Output Disabled, Option A Output Enabled, Option C Output Disabled, Option C Operating Temperature Package Size
1] 2] 3] 4] 5] 6] 7]
7 5
IOUT tR tF SYM J J J J 45 50 0.1 0.12 2.5 16 -60 VC ZIN BW VIH VIL VIL VIH TOP 0.3 75 50 Enable/Disable 0.7*VDD
20 500 500 55 0.250 0.300 3.0 24 -50 3.0
mA ps ps % ps-rms ps-rms ps ps dBc V K kHz V V
Jitter (50 kHz - 80 MHz BW)155.52MHz5
0.3*VDD 0.2*VDD 0.7*VDD 0/70 or -40/85 5.0 x 7.5 x 2.0
C mm
The VS-702 power supply should be filtered, eg, 0.1 and 0.01uF to ground See Standard Frequencies and Ordering Information tables for more specific information Parameters are tested with production test circuit below (Fig 1). Measured from 20% to 80% of a full output swing (Fig 2). Integrated across stated bandwidth. Tested with Vc = 0.3V to 3.0V unless otherwise stated in part description Broadband Period Jitter measured using Lecroy Wavemaster 8600A 6 GHz Oscilloscope, 25K samples taken. See application note.
Fig 1: Test Circuit
Fig 2: LVPECL Waveform
tR tF SYM = 100 x tA / tR
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tA tR
Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
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Outline Drawing & Pad Layout
6 5 4
XXX.XXXX VS702 YWW VDUGLA CCC-CCCC XXX.XX 35.328 VI YWW XXXMXXX
1 2 3
Dimensions in inches (mm)
Table 2. Pin Out Pin
1 2 3 4 5 6
Symbol VC
OE GND Output COutput
Function
VCXO Control Voltage Enable/Disable **See Ordering Options** Case and Electrical Ground Output Complementary Output Power Supply Voltage (3.3V 10%)
VDD
Typical Phase Noise
Typical Gain
VS-702 @ 622.08 MHz
200 120
150 110 100 100 50
Gain (ppm/V) Pull (ppm)
0 0 -50 0.5 1 1.5 2 2.5 3
90
Series1 Series2
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80 -100 70 -150
-200 Vc (volts)
60
Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
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Suggested Output Load Configurations
The VS-702 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 3. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme as shown in Figure 5. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems.
Figure 3 Standard PECL Output Configuration
Figure 4 Single Resistor Termination Scheme Resistor values are typically 120 to 240 ohms
Figure 5 Pull-Up Pull-Down Termination
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow simulation. The VS-702 family is capable of meeting the following qualification tests: Table 3. Environmental Compliance Parameter
Mechanical Shock Solderability Gross and Fine Leak Resistance to Solvents Moisture Sensitivity Level Contact Pads Mechanical Vibration
Conditions
MIL-STD-883, Method 2007
MIL-STD-883, Typical Characteristics - Phase Noise Method 2002
MIL-STD-883, Method 2003 MIL-STD-883, Method 1014 MIL-STD-883, Method 2015 MSL 1 Gold over Nickel
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Permanent damage is also possible if OD or Vc is applied before Vcc. Table 4. Absolute Maximum Ratings Parameter
Power Supply Output Current Voltage Control Range Storage Temperature Soldering Temp/Time www..com
Symbol
VDD IOUT VC TS TLS
Ratings
0 to 6 25 0 to VDD -55 to 125 260 / 40
Unit
V mA V C C / sec
Although ESD protection circuitry has been designed into the VS-702 proper precautions should be taken when handling and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing and design protection evaluation. Table 5. ESD Ratings Model
Human Body Model Charged Device Model
Minimum
500V 500V
Conditions
MIL-STD-883, Method 3015 JESD22-C101
Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
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IR
IR Reflow
Table 6. Reflow Profile (IPC/JEDEC J-STD-020C) Parameter
PreHeat Time Ts-min Ts-max Ramp Up Time Above 217 C Time To Peak Temperature Time at 260 C Ramp Down
Symbol
tS
Value
60 sec Min, 180 sec Max 150C 200C 3 C/sec Max 60 sec Min, 150 sec Max 480 sec Max 20 sec Min, 40 sec Max 6 C/sec Max
RUP tL T25C to peak tP RDN
The device is qualified to meet the JEDEC standard for Pb-Free assembly. The temperatures and time intervals listed are based on the Pb-Free small body requirements. The VS-702 device is hermetically sealed so an aqueous wash is not an issue. Termination Plating: Electroless Gold Plate over Nickel Plate
Tape & Reel (EIA-481-2-A)
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Table 7. Tape and Reel Information Tape Dimensions (mm) Dimension Tolerance
VS-702
Reel Dimensions (mm) Po Typ
4
W Typ
16
F Typ
7.5
Do Typ
1.5
P1 Typ
8
A Typ
178
B Min
1.5
C Typ
13
D Min
20.2
N Min
50
W1 Typ
16.4
W2 Max
22.4
# Per Reel
200
Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
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Table 8. Standard Output Frequencies (MHz)
155M520000 240M000000 320M000000 491M520000 635M040000 690M569200 800M000000 156M250000 245M760000 324M000000 500M000000 637M500000 693M483000 901M120000 160M000000 250M000000 350M000000 531M250000 640M000000 704M380600 1000M00000 162M000000 260M000000 375M000000 532M000000 644M531300 707M352700 175M000000 268M800000 384M000000 533M000000 657M421900 720M000000 187M500000 300M000000 389M600000 537M600000 666M514300 742M434700 200M000000 311M040000 400M000000 622M080000 669M326600 768M000000 212M500000 312M500000 480M000000 625M000000 672M162700 796M875000
Ordering Information
VS-702- E C E - K X A N - xxxMxxxxxx
Product Family VS: VCSO Package 702: 5 x 7.5 x 2.0 mm Input E: 3.3 Vdc 10% Output C: LVPECL (45/55% Symmetry) D: LVDS (45/55% Symmetry) Operating Temperature T: 0/70C E: -40/85C
*Note: not all combination of options are available. Other specifications may be available upon request.
Frequency in MHz Other (Future Use) N: Standard Enable/Disable A: Enable High C: Enable Low Stability X: Standard E: 20ppm Temperature Stability Absolute Pull Range K: 50ppm
Example: VS-702-ECE-KXAN-622M080000
For Additional Information, Please Contact
USA:
Vectron International 267 Lowell Road Hudson, NH 03051 Tel: 1.888.328.7661 www..com Fax: 1.888.329.8328
Europe:
Vectron International Landstrasse, D-74924 Neckarbischofsheim, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30
Asia:
Vectron International 1F-2F, No 8 Workshop, No 308 Fenju Road WaiGaoQiao Free Trade Zone Pudong, Shanghai, China 200131 Tel: 86.21.5048.0777 Fax: 86.21.5048.1881
Disclaimer
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Rev: 1/10/2009 Vectron International * 267 Lowell Road, Hudson, NH 03051 * Tel: 1-88-VECTRON-1 * http://www.vectron.com
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